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LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP
FEATURES
s
DESCRIPTIO
s s s s s s s s s
Smallest Pin-Compatible Dual DACs: LTC2602: 16-Bits LTC2612: 14-Bits LTC2622: 12-Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 300A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk between DACs (30V) High Rail-to-Rail Output Drive (15mA) Double-Buffered Data Latches Pin-Compatible 10-Bit Version (LTC1661) Tiny 8-Lead MSOP Package
The LTC(R)2602/LTC2612/LTC2622 are dual 16-,14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs, in a tiny 8-lead MSOP package. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish advanced performance standards for output drive, crosstalk and load regulation in singlesupply, voltage output multiples. The parts use a simple SPI/MICROWIRETM compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. The LTC2602/LTC2612/LTC2622 incorporate a poweron reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale, and after powerup, they stay at zero scale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
LTC2602
REGISTER REGISTER REGISTER REGISTER
Differential Nonlinearity (DNL)(LTC2602)
1.0
16-BIT DAC B 5 VOUT B
VOUT A 8
16-BIT DAC A
0.8 0.6 0.4
ERROR (LSB)
0.2 0 -0.2 -0.4
GND 7
6 VCC
CS/LD 1
CONTROL LOGIC
DECODE 4 REF
-0.6 -0.8
SCK 2
24-BIT SHIFT REGISTER
3 SDI
-1.0
2602 BD01
U
VCC = 5V VREF = 4.096V 0 16384 32768 CODE 49152 65535
2602 TA01
W
U
2602f
1
LTC2602/LTC2612/LTC2622 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW CS/LD SCK SDI REF 1 2 3 4 8 7 6 5 VOUT A GND VCC VOUT B
Any Pin to GND ........................................... - 0.3V to 6V Any Pin to VCC ........................................................ -6V to 0.3V Maximum Junction Temperature ......................... 125C Operating Temperature Range LTC2602C/LTC2612C/LTC2622C .......... 0C to 70C LTC2602I/LTC2612I/LTC2622I .......... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 300C/W
LTC2602CMS8 LTC2602IMS8 LTC2612CMS8 LTC2612IMS8 LTC2622CMS8 LTC2622IMS8 MS8 PART MARKING LTACX LTACY LTACZ LTADA LTADB LTADC
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity Load Regulation VCC = 5V, VREF = 4.096V (Note 2) VCC = 5V, VREF = 4.096V (Note 2) VCC = 5V, VREF = 4.096V (Note 2) VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.5V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking ZSE VOS Zero-Scale Error Offset Error VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient VCC = 5V, VREF = 4.096V
q q q q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 12 12
LTC2622 TYP MAX
MIN 14 14
LTC2612 TYP MAX
MIN 16 16
LTC2602 TYP MAX
UNITS Bits Bits
0.5 0.75 4 3 0.1 0.2 0.2 0.4 1 1 5
1 16 0.5 0.5 1 1 9 9 12 0.4 0.65 0.9 1.3 1 1 5
1 64 2 2 4 4 9 9
0.025 0.125 0.05 0.125 0.05 0.1 1 1 5 0.1 0.7 3 0.25 0.25 9 9
LSB/mA LSB/mA LSB/mA LSB/mA mV mV V/C %FSR ppm/C
VCC = 5V, VREF = 4.096V Code = 0 q VCC = 5V, VREF = 4.096V, (Note 7) q
0.1 0.7 3
0.1 0.7 3
2
U
LSB LSB
2602f
W
U
U
WW
W
LTC2602/LTC2612/LTC2622
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PSRR ROUT PARAMETER Power Supply Rejection Ratio DC Output Impedance DC Crosstalk (Note 4) CONDITIONS VCC = 5V 10% VREF = VCC = 5V, Midscale; -15mA IOUT 15mA VREF = VCC = 2.5V, Midscale; -7.5mA IOUT 7.5mA Due to Full Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.5V, VREF = 2.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current, Power Down Mode All DACs Powered Down Positive Supply Voltage Supply Current For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 2.5V to 5.5V VIN = GND to VCC (Note 6) LTC2622 TYP MAX 7
q q q q q q q q
ELECTRICAL CHARACTERISTICS
LTC2602/LTC2612/LTC2622 MIN TYP MAX -80 0.05 0.05 30 16 4 15 15 7.5 7.5 0 44 64 23 0.001 2.5 0.7 0.6 0.35 0.10 2.4 2.0 0.8 0.6 0.5 1 8 LTC2602 TYP MAX 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15 1 5.5 1.3 1 1 1 34 38 20 28 60 60 50 50 VCC 80 0.15 0.15
UNITS dB V V/mA V mA mA mA mA V k pF A V mA mA A A V V V V V A pF
ISC
Short-Circuit Output Current
Normal Mode
q
Power Supply
q q q q q
Digital I/O VIH VIL Digital Input High Voltage Digital Input Low Voltage
q q q q q q q
ILK CIN
Digital Input Leakage Digital Input Capacitance
SYMBOL PARAMETER AC Performance ts Settling Time (Note 8)
CONDITIONS 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits)
MIN
MIN
LTC2612 TYP MAX 7 9 2.7 4.8 0.80 1000 12 180 120 100 15
MIN
UNITS s s s s s s V/s pF nV * s kHz nV/Hz nV/Hz VP-P
2602f
Settling Time for 1LSB Step (Note 9) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth Output Voltage Noise Density Output Voltage Noise
2.7
At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz
en
0.80 1000 12 180 120 100 15
3
LTC2602/LTC2612/LTC2622 TI I G CHARACTERISTICS
SYMBOL t1 t2 t3 t4 t5 t6 t7 t10 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle VCC = 2.5V to 5.5V
q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Note 6)
CONDITIONS LTC2602/LTC2612/LTC2622 MIN TYP MAX 4 4 9 9 10 7 7 7 50 UNITS ns ns ns ns ns ns ns ns MHz
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at midscale, unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602) Integral Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2602 G20
VCC = 5V VREF = 4.096V
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2602 G21
INL (LSB)
4
UW
UW
Note 5: RL = 2k to GND or VCC at the output of the DAC not being tested. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2602), code 64 (LTC2612) or code 16 (LTC2622), and at fullscale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped LBS between half scale and half scale -1. Load is 2k in parallel with 200pF to GND.
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 16 8 0 -8 -16 -24 VCC = 5V VREF = 4.096V 32 24
INL vs Temperature
VCC = 5V VREF = 4.096V
INL (POS)
INL (NEG)
-32 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2602 G22
2602f
LTC2602/LTC2612/LTC2622 TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602) DNL vs Temperature
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -16 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -24 -32 0 1 2 3 VREF (V) 4 5
2602 G24
VCC = 5V VREF = 4.096V DNL (POS) INL (LSB)
0 -8 INL (NEG)
DNL (LSB)
DNL (NEG)
Settling to 1LSB
VOUT 100V/DIV 9.7s CS/LD 2V/DIV
VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
(LTC2612) Integral Nonlinearity (INL)
8 6 4 DNL (LSB) INL (LSB) 2 0 -2 -4 -6 -8 0 4096 8192 CODE 12288 16383
2602 G28
VCC = 5V VREF = 4.096V
UW
2602 G23
INL vs VREF
32 24 16 8 INL (POS) 0.5 VCC = 5.5V 1.0 1.5
DNL vs VREF
VCC = 5.5V
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
0
1
2 3 VREF (V)
4
5
2602 G25
Settling of Full-Scale Step
VOUT 100V/DIV
12.3s
CS/LD 2V/DIV
2s/DIV
2602 G26
5s/DIV VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS SETTLING TO 1LSB
2602 G27
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16383
2602 G29
Settling to 1LSB
VCC = 5V VREF = 4.096V
VOUT 100V/DIV
CS/LD 2V/DIV
8.9s 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2602 G30
2602f
5
LTC2602/LTC2612/LTC2622 TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2622) Integral Nonlinearity (INL)
2.0 1.5 1.0 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2602 G31
VCC = 5V VREF = 4.096V
(LTC2602/LTC2612/LTC2622) Current Limiting
0.10 0.08 0.06 0.04
VOUT (V)
CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V
0.4
OFFSET ERROR (mV)
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 10 -40 -30 -20 -10 0 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V
VOUT (mV)
Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3
OFFSET ERROR (mV)
-30
-10 10 30 50 TEMPERATURE (C)
6
UW
70
2602 G04
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2602 G32
Settling to 1LSB
VCC = 5V VREF = 4.096V
6.8s VOUT 1mV/DIV
CS/LD 2V/DIV
2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2602 G33
Load Regulation
1.0 0.8 0.6 2 1 0 -1 -2 CODE = MIDSCALE 3
Offset Error vs Temperature
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 VREF = VCC = 3V VREF = VCC = 5V
-3 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2602 G01
2602 G02
2602 G03
Gain Error vs Temperature
3 2 1 0 -1 -2 -3
Offset Error vs VCC
0.2 0.1 0 -0.1 -0.2 -0.3
90
-0.4 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2602 G06
2602 G05
2602f
LTC2602/LTC2612/LTC2622 TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602/LTC2612/LTC2622) Gain Error vs VCC
0.4 0.3 0.2
GAIN ERROR (%FSR)
0.1
ICC (nA)
0 -0.1 -0.2
-0.3 -0.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
2602 G07
Midscale Glitch Impulse
VOUT 10mV/DIV 12nV-s TYP
VOUT (V)
CS/LD 5V/DIV
2602 G10
2.5s/DIV
Supply Current vs Logic Voltage
2.4 2.3 2.2 2.1 ICC (mA) 2.0 1.9 1.8 1.7 1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC
dB
UW
2602 G13
ICC Shutdown vs VCC
450 400 350 300 250 200 150 100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
2602 G08
Large-Signal Settling
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2602 G09
Power-On Reset Glitch
5.0 4.5 4.0
Headroom at Rails vs Output Current
5V SOURCING
VCC 1V/DIV 4mV PEAK 4mV PEAK VOUT 10mV/DIV 250s/DIV
2602 G11
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 456 IOUT (mA) 7 8 9 10 3V SINKING 5V SINKING 3V SOURCING
2602 G12
Exiting Power-Down to Midscale
0
Multiplying Frequency Response
-3 -6 -9 -12 -15
VCC = 5V VREF = 2V VOUT 0.5V/DIV ONE DAC IN POWER DOWN MODE CS/LD 5V/DIV
-18 -21 -24 -27 -30 -33 -36 1k VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 10k 100k FREQUENCY (Hz) 1M
2602 G16
2.5s/DIV
2602 G14
2602f
7
LTC2602/LTC2612/LTC2622 TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602/LTC2612/LTC2622) Output Voltage Noise, 0.1Hz to 10Hz Short-Circuit Output Current vs VOUT (Sinking)
0mA
10mA/DIV
0mA
0
1
2
3
456 SECONDS
7
8
9
10
VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV
2602 G18
10mA/DIV
VOUT 10V/DIV
8
UW
Short-Circuit Output Current vs VOUT (Sourcing)
VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 1V/DIV
2602 G19
2602 G17
2602f
LTC2602/LTC2612/LTC2622
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 3): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2602/LTC2612/LTC2622 accept input word lengths of either 24 or 32 bits. REF (Pin 4): Reference Voltage Input. 0V VREF VCC. VOUT B and VOUT A (Pins 5 and 8): DAC Analog Voltage Outputs. The output range is 0 - VREF. VCC (Pin 6): Supply Voltage Input. 2.5V VCC 5.5V. GND (Pin 7): Analog Ground.
BLOCK DIAGRA
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
DAC REGISTER
VOUT A 8
GND 7
CS/LD 1
SCK 2
TI I G DIAGRA
SCK
SDI t5 CS/LD t7
W
W
U
U
UW
U
DAC A
DAC B
5 VOUT B
6 VCC
CONTROL LOGIC
DECODE 4 REF
24-BIT SHIFT REGISTER
3 SDI
2602 BD
t1 t2 1 t3 2 t4 3 23 t6 24 t10 C3 C2 C1 D1 D0
2602 F01
Figure 1
2602f
9
LTC2602/LTC2612/LTC2622
OPERATIO
Power-On Reset
The LTC2602/LTC2612/LTC2622 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2602/ LTC2612/LTC2622 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made smaller by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 4) should be kept within the range - 0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 6) is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = N VREF 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 4).
Table 1.
COMMAND* C3 C2 C1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 ADDRESS (n)* A3 A2 A1 0 0 0 0 0 0 1 1 1 C0 0 1 0 1 0 1 A0 0 1 1
*Command and address codes not shown are reserved and should not be used.
10
U
Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, activating the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2602, LTC2612 and LTC2622 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two outputs are needed. When in power-down, the buffer amplifiers, bias circuits and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the
2602f
Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation
DAC A DAC B All DACs
LTC2602/LTC2612/LTC2622
OPERATIO
INPUT WORD (LTC2602)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2602 TBL01
INPUT WORD (LTC2612)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (14 BITS + 2 DON'T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2602 TBL02
INPUT WORD (LTC2622)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB DATA (12 BITS + 4 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2602 TBL03
output pins are passively pulled to ground through individual 90k resistors. Input- and DAC-register contents are not disturbed during power-down. Either channel or both channels can be put into powerdown mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 50% for each DAC powered down; the effective resistance at REF (pin 4) rises accordingly, becoming a high-impedance input (typically > 1G) when both DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If one of the two DACs is in a powered-down state prior to the update command, the power-up delay is 5s. If, on the other hand, both DACs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power up delay time is 12s (for VCC = 5V) or 30s (for VCC = 3V).
U
X X X X X X
Voltage Outputs Each of the two rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.050 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF.
2602f
11
LTC2602/LTC2612/LTC2622
OPERATIO
Board Layout
The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer.
12
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The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.050), and will degrade DC crosstalk. Note that the LTC2602/LTC2612/LTC2622 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
2602f
SCK 2 7 13 14 17 D7
YYYY F02a
1 10 21 D3 D2 D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 22 16 20 C1 ADDRESS WORD C0 A3 A2 A1 A0 D15
3 4 5 6 8 9 15 19
SDI
C3
C2
COMMAND WORD
24-BIT INPUT WORD
Figure 2a. LTC2602 24-Bit Load Sequence (Minimum Input Word) LTC2612 SDI Data Word 14-Bit Input Code + 2 Don't Care Bits LTC2622 SDI Data Word 12-Bit Input Code + 4 Don't Care Bits
CS/LD 6 7 13 14 A2 ADDRESS WORD A1 A0 A3 X COMMAND WORD X C3 C2 C1 C0 8 9 10 11 12 16 15 X 17 D15 18 D14 19 D13 20 D12 21 D11 22 D10 23 D9 24 D8 25 D7 DATA WORD 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
2602 F02b
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
Figure 2b. LTC2602 32-Bit Load Sequence LTC2612 SDI Data Word 14-Bit Input Code + 2 Don't Care Bits LTC2622 SDI Data Word 12-Bit Input Code + 4 Don't Care Bits
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LTC2602/LTC2612/LTC2622
OPERATIO
CS/LD
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2602f
LTC2602/LTC2612/LTC2622
OPERATIO
OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) INPUT CODE (b)
2600 F03
0V NEGATIVE OFFSET
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
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VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 65, 535
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LTC2602/LTC2612/LTC2622
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.42 0.038 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT DETAIL "A" 0 - 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4)
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.127 0.076 (.005 .003)
MSOP (MS8) 0603
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 0.65 (.0256) BSC 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.0205) REF 0.53 0.152 (.021 .006) DETAIL "A" 1 1.10 (.043) MAX 23 4 0.86 (.034) REF 0.65 (.0256) BSC
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LTC2602/LTC2612/LTC2622 RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1661 LTC1821 LTC2600/LTC2610/ LTC2620 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 10-Bit VOUT DAC in 8-Lead MSOP Package Parallel 16-Bit Voltage Output DAC Octal 16/14/12-Bit Rail-to-Rail DACs in 16-Lead SSOP COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60A per DAC, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step 250A per DAC, 2.5V to 5.5V Supply Range Rail-to-Rail Output
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16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 1003 1K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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